Gate 2006 pyq CAO |A pipelined processor uses a 4-stage instruction pipeline with the following
Автор: Gate CS pyqs - the other way [Eng]
Загружено: 2022-04-30
Просмотров: 1365
Описание:
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S – R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
ADD R5,R0,R1 ;R5←R0 + R1
MUL R6,R2,R5 ;R6←R2 * R5
SUB R5,R3,R6 ;R5←R3 -R6
DIV R6,R5,R4 ;R6←R5/R4
STORE R6,X ;X←R6
The IF, ID and WB stages take 1 clock cycle each. The EX stage takes 1 clock cycle each for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV operations. Operand forwarding from the EX stage to the ID stage is used. The number of clock cycles required to complete the sequence of instructions is
(A) 10
(B) 12
(C) 14
(D) 16
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