Gate 2007 pyq CAO | Consider a pipelined processor with the following four stages
Автор: Gate CS pyqs - the other way [Eng]
Загружено: 2022-04-30
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Описание:
Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 {---- R0 + R1
MUL R4, R3, R2 R4 {---- R3 * R2
SUB R6, R5, R4 R6 {---- R5 - R4
(A) 7
(B) 8
(C) 10
(D) 14
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