4-Stage Pipeline:RAW, WAR, WAW Dependencies in Arithmetic ins how many RAW,WAR,&WAW dependency exist
Автор: MCA ZZ
Загружено: 2024-01-24
Просмотров: 49
Описание:
Instructions:
ADD R5, R0, R1 → R5 = R0 + R1
MUL R6, R2, R5 → R6 = R2 * R5
SUB R5, R3, R6 → R5 = R3 - R6
DIV R6, R5, R4 → R6 = R5 / R4
STORE X, R6 → X = R6
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), and Write Back (WB). Arithmetic operations as well as load and store operations are carried out in the EX stage. The sequence of instructions corresponds to the statement:
X = (s - r * (p + q)) / t
The values of variables p, q, r, s, and t are available in registers R0, R1, R2, R3, and R4, respectively, before the execution of the instruction sequence.
The instructions are:
ADD R5, R0, R1 → R5 = R0 + R1
MUL R6, R2, R5 → R6 = R2 * R5
SUB R5, R3, R6 → R5 = R3 - R6
DIV R6, R5, R4 → R6 = R5 / R4
STORE R6, X → X = R6
Question:
The number of Read-After-Write (RAW), Write-After-Read (WAR), and Write-After-Write (WAW) data dependencies in the sequence of instructions are, respectively?
A pipelined with 4 stage executes the
ADD R5, R0, R1
MUL R6, R2, R5
SUB R5, R3, R6
DIV R6, R5, R4
STORE X, R6
Given X = (s-r*(p + q))/ t with p,q,r,s,t R0-R4,how many RAW,WAR,&WAW dependencies exist
#codingzz #mca #pipelining #unit5 #coa #mcacoding #datadependency #raw #war #waw
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