Gate 2005 pyq CAO | A 5 stage pipelined CPU has the following sequence of stages:IF — Instruction f
Автор: Gate CS pyqs - the other way[Hin]
Загружено: 2022-05-01
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Описание:
A 5 stage pipelined CPU has the following sequence of stages:
IF — Instruction fetch from instruction memory,
RD — Instruction decode and register read,
EX — Execute: ALU operation for data and address computation,
MA — Data memory access - for write access, the register read
at RD stage is used,
WB — Register write back.
Consider the following sequence of instructions:
I1 : L R0, 1oc1; R0 {=== M[1oc1]
I2 : A R0, R0; R0 {=== R0 + R0
I3 : S R2, R0; R2 {=== R2 - R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1 ?
(A) 8
(B) 10
(C) 12
(D) 15
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