ISERDESE3 Xilinx Deserializer – UltraScale & UltraScale+ SERDES Block Explained
Автор: Paul K
Загружено: 2025-12-04
Просмотров: 130
Описание:
In this video, we dive into the ISERDESE3 primitive for Xilinx UltraScale and UltraScale+ FPGAs. Learn how this SERDES hardware block converts high-speed serial data into parallel data, supporting DDR deserialization and ratios of 2, 4, or 8.
We cover:
• How the 8-bit shift register and CLKDIV work in DDR mode
• The built-in 8-entry FIFO for clock domain crossing
• Key differences from ISERDESE2, including the absence of a native BITSLIP input
• SHIFTIN/SHIFTOUT cascading for wider deserialization (up to 14 bits)
• Using a gearbox to handle unsupported parallel widths
• Timing diagrams and VHDL insights
Perfect for FPGA designers looking to understand high-speed deserialization and parallel data capture in hardware.
VHDL Code for this video: https://github.com/pkerstetter/ISERDESE3
📌 Related Video: “Bit Alignment and Bit Slipping in FPGAs”
📘 The Joy of Doing Less
Unrelated to this video, but I’ve written a short book on simplicity and doing less.
https://www.amazon.com/Joy-Doing-Less...
#Xilinx #ISERDESE3 #FPGA #SERDES #Ultrascale #Deserialization #Gearbox #DDR #VHDL #HighSpeedInterface
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