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Distributed Simulation for Chiplets (3× Faster with Xcelium)

Xcelium Distributed Simulation

Cadence Xcelium

Chiplet Verification

Multi-Die Simulation

3DIC Verification

UCIe Interface

PCIe Chiplet

Distributed Simulation EDA

UVM Testbench Reuse

Shift-Left Verification

Verisium Debug

Cadence Whiteboard

Xcelium App

Multi-Die Verification

Chiplet Simulation

UCIe PCIe Interfaces

UVM Reuse

Verisium Debug Integration

Early Bug Discovery

Interposer Ready

Multi-Die SoC

Chiplet Verification Flow

UCIe PCIe D2D

Автор: Cadence Design Systems

Загружено: 2025-09-23

Просмотров: 338

Описание: Chiplet‑based, multi‑die SoCs let teams push performance and yield — but they also strain traditional verification.

When you move from a single‑die to an N‑die system, your UVM testbench grows, your simulation database explodes, and your farm/infrastructure gets stressed.

In this Cadence Whiteboard session, host Aneka Sunanda welcomes Prashant Teotia (Director, Product Engineering, Cadence) to explain how the Cadence Xcelium™ Distributed Simulation App links per‑die testbenches with virtual channels — so you can reuse monolithic TBs, run each die in parallel, and see up to 3× faster sims (with 2–5× improvements discussed for some two‑die cases) while keeping LRM‑compliant system behavior.

Why verification slows down without distribution?

1. TB extension overhead: Moving from 1 die → 2/3/4 dies multiplies BFMs/agents, sequences, and monitors across interfaces.
2. Performance hit: One big integrated snapshot often means longer runtimes, bigger memory footprints, and regressions that don’t scale.
3. Compute cost: Multi‑die runs can demand bigger hosts (memory/CPU), lowering job throughput or inflating infrastructure cost.

What Xcelium Distributed Simulation does?

• Reuse existing TBs: Keep each die’s original UVM testbench; map RX/TX interface signals using simple $distributed APIs.
• Create virtual channels: The tool stitches dies into one system simulation with LRM‑compliant connections — no heavy integrated top required.
• Parallelize runs: Each die simulates on separate machines, preserving a single‑system view while distributing load.
• Speed & scale: Teams have observed ~2–5× improvements discussed (and up to 3× commonly cited) with multiple dies, plus lower farm pressure.
• Shift‑left: Start multi‑die verification earlier—before full interposer/top‑level integration — by leveraging single‑die TBs.

Debug that spans dies!

Integrated with Verisium™ Debug, you can visualize which dies are connected, drill down into die‑to‑die signal maps, and hop between databases in one GUI — ideal when a failure on D2 is rooted in D1.

Chapters (timestamps) :

(00:00) — Why multi‑die verification needs a rethink
(00:02) — Welcome to Cadence Whiteboard (host intro)
(00:08) — Guest intro: Prashant Teotia (Cadence)
(00:22) — What the Xcelium Distributed Simulation App is?
(01:05) — From single die to multi‑die: TB explosion explained
(03:00) — Performance & compute challenges as dies scale
(04:27) — How distribution works conceptually
(05:25) — Reusing existing TBs; mapping RX/TX with $distributed APIs
(06:50) — Virtual channels: system semantics without an integrated top
(07:12) — Performance gains discussed: ~2–5×; impact on throughput
(08:28) — Farm/infrastructure: load distribution, similar per‑die specs
(09:59) — Shift‑left: run multi‑die early, find bugs sooner
(11:23) — Verisium Debug: multi‑DB navigation & signal maps
(13:06) — Closing takeaways

Key learning points :

• Reuse single‑die UVM to accelerate multi‑die bring‑up
• Stitch dies with virtual channels via simple $distributed APIs
• Achieve up to 3× faster sims (with 2–5× discussed) and distribute farm load
• Use Verisium Debug to hop across die databases and shorten root‑cause

Who should watch?

• Verification leads
• DV engineers
• SoC/3D‑IC architects
• Program managers adopting chiplets, UCIe/PCIe/custom D2D links, and system‑in‑package flows.

Get started / Learn more :

• Website: https://www.cadence.com
• Free Trials: https://www.cadence.com/en_US/home/to...

---------------------------------------------------------------------------------------------------------------------------------------------------------------

Connect with Cadence :

• YouTube:    / @cadencedesignsystems  
• LinkedIn:   / cadence  
• Facebook:   / cadencedesign  
• Twitter/X:   / cadence  
• Instagram:   / cadencedesignsystems  

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About Cadence :

Cadence is a global leader in electronic systems design, applying its Intelligent System Design™ strategy to deliver software, hardware, and IP that turn design concepts into reality.

Cadence® customers are among the world’s most innovative companies, creating breakthrough products — from chips to boards to full systems—across markets including hyperscale computing, 5G, automotive, aerospace, mobile, consumer, industrial, and healthcare.

Recognized by Fortune as one of the 100 Best Companies to Work For nine consecutive years.

Learn more at https://www.cadence.com.


#ucie #pcie #verification #uvm #shiftleft

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Distributed Simulation for Chiplets (3× Faster with Xcelium)

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