Old School cache coherence-a snooping system for a multicore processor based on CVA6 (M. Giacometti)

Описание: For many years now the computational power required by modern applications can only be offered by a collection of CPUs working together in a multicore processor. For these CPUs to process information correctly, it is necessary to implement mechanisms which guarantee that each core always uses an up-to-date version of the data: cache coherence protocols have been developed with this purpose. Years ago, when silicon technology could support the integration of only a handful of CPUs per chip, cache coherence was achieved by implementing bus snooping mechanisms; nowadays the propensity is to make use of directory-based cache coherence mechanisms, which guarantee excellent scalability, at the expense speed. This trend can be confirmed also by looking at the existing open-source implementations: there is not a single snooping mechanism. This is a problem, because many real-world scenarios would benefit from a low latency cache coherence unit, for example for all processors integrating a limited number of CPUs. With Culsans our goal is to cover this gap, by developing an open-source, tightly-coupled, low latency cache coherence unit for a quad-core processor based on the popular RISC-V CPU CVA6. In this presentation we show the architecture and the performance of the proposed implementation.