Simple Cache Memory and Graphics for RISC-V RV32IC (FPGA)
Автор: Jin-Lien Lin
Загружено: 2022-10-16
Просмотров: 839
Описание:
This is an experiment of adding a simple 8KB instruction cache to my tiny RISC-V system and see how much performance improvement I could get, after I added SDRAM in the previous project update. A simple graphics demo is given at the end of the video as a performance benchmark.
Cross-compiler used in this project:
https://github.com/xpack-dev-tools/ri...
Previous update for adding SDRAM to the system:
• RISC-V RV32IC booting from a FAT32 SD card...
Previous update for Dhrystone run:
• Initial Dhrystone Run on RISC-V RV32IC (FPGA)
Повторяем попытку...
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