SiC Testing 2.8MHz SSTC Music

Описание: This is the 1200V 80mohm version of the SiC fet I killed on this setup by wacking out the tuning too much so I'm not going to push it very hard yet. The slower cascode seems a little less susceptible to the ringing and with the low gate voltage I can speed up the fall time a little with a fast reverse parallel switching diode or just remove the external gate resistance almost completely. At higher gate voltage this would probably result in more ringing and larger undershoot. Part of getting the best audio with this PLL setup revolves around multiple variables and it seems easy only until trying to get the best quality. To try stereo I could probably just run a splitter and feed two circuits a separate channel but I don't think it would sound better than a single coil running both channels when buck modulated. Stereo effect only becomes useful when there is some distance between the speakers which makes a compact dual-coil build less logical.

An issue I see with using these cheap CD4046BE chips is that the VCO creates a lot of noise when driving the UCC. It doesn't output a perfect square wave because the VCO ripple is superimposed upon it, and the gate driver translates this into a duty cycle which is a little over 50%. This is no issue with my class e using CT feedback and no PLL and the signal is rock solid and clean. IDK if this is just an issue with the specific clone chip or the wiring but you can see the imperfect signal slightly shifting around even with no audio signal forcing the VCO to do it. Something like that could probably be fixed here with this fixed frequency setup by actually putting the schmitt trigger after the PLL.

Once I have eventually made some kind of super low inductance layout with better drive circuitry I can compare those results with what I was doing here using a short jumper wire protoboard layout.