A UVM Testbench for Exploring Design Margins of Analog/Mixed-Signal Circuits

Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

Catching the Elusive Voltage Spike with Analog/Mixed-Signal SVA/PSL Assertions

DVD - Lecture 10: Packaging and I/O Circuits

Harnessing the Power of UVM for AMS Verification with XMODEL (Part 1)

[CVPR 2025] EfficientViM: Efficient Vision Mamba with Hidden State Mixer based State Space Duality

Webinars

DVD - Lecture 10c: I/O Circuits - Analog IOs, ESD Protection, Pad Configurations

[1/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Overview and Introduction to XMODEL

A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers

Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: A Pipelined ADC

VLSI - Lecture 6a: Interconnect (Capacitance)

[4/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Electrical Layer Modeling (Part 3)

DVD - Lecture 8: Clock Tree Synthesis

Harnessing the Power of UVM for AMS Verification with XMODEL (Part 2)

Advanced Process Technologies - Part 3: FinFET Layout

NIEMIECKI TARTAK z czasów wojny. NIEZNISZCZALNY Miejscowość: Łupianka Stara

Low-Dropout (LDO) Regulator Modeling with XMODEL | XMODEL - Scientific Analog

[5/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Logical Layer Modeling & Simulation

VLSI - Lecture 6b: Resistance and Interconnect Modeling

[2/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Electrical Layer Modeling (Part 1)