4 way Set Associative Mapping Cache Tamil / PG TRB ComputerScience / TRB Polytechnic CSE / PG TRB CS

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4 way Set Associative Mapping Cache Computer Architecture Tamil / PG TRB ComputerScience / TRB Polytechnic CSE / PG TRB CS

Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively
(A) 9, 6, 5 (B) 7, 7, 6
(C) 7, 5, 8 (D) 9, 5, 6