Stop hoping for the best: Fully verify signal integrity of SerDes designs before manufacture

Описание: “Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into the layout that cause issues during lab testing and result in costly, time-consuming respins.

This video explores why this happens and how to address it through a multifaceted approach that involves meticulous consideration of board fabrication nuances such as layer thickness and conductivity, and ensuring simulations actually model the board as implemented (instead of the board as intended) by using automated post-layout verification that extracts, models and analyzes all the design's serial channels instead of only a select few. This session was originally recorded live in January 2024.

0:29 The case for post-route verification
4:13 Why do we run simulations in the first place?
8:36 How do people end up designing one thing and building another?
15:08 Traditional post-layout verification
21:52 Post-route serial link verification flow
37:03 Summary
39:38 Signal integrity resources and links
41:55 Q&A with audience

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