How to instantiate a Verilog module, part 2, bus signals

Описание: Module instantiation is often a tricky subject for students learning a hardware description language. It's often easier to understand block schematic diagrams as they provide a visual reference for wiring connections. We create a block schematic solution and then use it to understand how to create the same system with Verilog. The Verilog solution explains using named instantiation to wire (connect) one Verilog module to another, with bus signals.