Introduction to Verilog HDL course

Описание: Lesson-1 Why verilog is a popular HDL    • #1 Why verilog is a popular HDL | properti...  
Lesson-2 Operators in verilog(part-1)    • #2  Operators in Verilog ( part -1 ) | How...  
Lesson-2 Operators in verilog(part-2)    • Operators in Verilog ( part -2 ) | How eac...  
Lesson-2 Operators in verilog(part-3)    • Operators in Verilog( Part-3)  | How each ...  
Lesson-3 Syntax in verilog    • #3  Syntax in Verilog  | Identifier, Numbe...  
Lesson-4 Data types in verilog    • #4 Data types in verilog | wire, reg, inte...  
Lesson-5 Vector and Array in verilog    • #5 {Error:check description} Vector and Ar...  
Lesson-6 Modules and port in verilog    • #6  Module and port declaration in verilog...  
Lesson-7 Gate level modelling in verilog    • #7  Gate level modeling and structural mod...  
Lesson-8 Dataflow Modeling in verilog    • #8  Data flow modeling in verilog | explan...  
Lesson-9 Behavioral Modeling in verilog    • #9  Behavioral modelling in verilog || Lev...  
Lesson-10 Structural Modeling in verilog    • #10  How to write verilog code using struc...  
Lesson-11 always block in verilog    • #11  always block in Verilog || procedural...  
Lesson-12 always block for combinational logic    • #12 always block for combinational logic |...  
Lesson-13 sequential logic in design    • #13{Mistake:check description}sequential l...  
Lesson-14 always block for sequential logic    • #14 always block for sequential logic || a...  
Lesson-15 Difference between latch and flip flop    • #15  Difference between Latch and Flip-flo...  
Lesson-16 Synchronous and Asynchronous RESET    • #16(MISTAKE-Read Description) Synchronous ...  
Lesson-17 Delays in verilog    • #17 Delays in verilog | Rise time, fall ti...  
Lesson-18 Timing control in verilog    • #18 Timing control in verilog | Delay base...  
Lesson-19 Blocking and Nonblocking assignment    • #19 Blocking vs Non Blocking assignment | ...  
Lesson-20 inter and intra assignment delay in verilog    • #20 Inter and intra assignment delay | gat...  
Lesson-21 Why delays are not synthesizable    • #21 Why delays are not synthesizsble in ve...  
Lesson-22 TESTBENCH writing in verilog    • #22 How to write TESTBENCH  in verilog || ...  
Lesson-23 Multiple always block in verilog    • #23 Multiple ALWAYS block in verilog | pro...  
Lesson-24 INITIAL block in verilog    • #24 INITIAL block in verilog | use of INIT...  
Lesson-25 Difference between INITIAL and ALWAYS block in verilog    • #25 Difference between ALWAYS and INITIAL ...  
Lesson-26 if else in verilog    • #26 if-else in verilog |conditional statem...  
Lesson-27 CASE statement in verilog    • #27 "case" statement in verilog | if-else ...  
Lesson-28 CASEX and CASEZ in verilog    • #28 casex vs casez in verilog | Explained ...  
Lesson-29 FOR loop in verilog    • #29 "for" loop in verilog || Hardware mean...  
Lesson-30 WHILE loop in verilog    • #30 "while" loop in verilog || Hardware me...  
Lesson-31 FOREVER in verilog    • #31 " forever " in verilog || How to gener...  
Lesson-32 REPEAT in verilog    • #32 " repeat " in verilog || realtime exam...  
Lesson-33 GENERATE in verilog    • #33 "generate" in verilog | generate block...  
Lesson-34 FORK-JOIN in verilog    • #34 " fork and join " in verilog || parall...  
Lesson-35 named block in verilog    • #35 Named block in verilog || verilog bloc...  
Lesson-36 TASK in verilog    • #36 (MISTAKE-Read Description) TASK in ver...  
Lesson-37 FUNCTION in verilog    • #37 (MISTAKE-Read Description) FUNCTION in...  
Lesson-38 WIRE vs REG in verilog    • #38 Wire vs Reg | when to use wire and reg...  
Lesson-39 FSM-MEALY state machine in verilog    • #39 Finite state machine(FSM) | Mealy stat...  
Lesson-40 FSM- MOORE state machine in verilog    • #40 Finite state machine(FSM) | Moore stat...  




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