Gate 2005 pyq DIGITAL | Consider the following circuit involving a positive edge triggered D FF.
Автор: Gate CS pyqs - the other way [Eng]
Загружено: 2022-07-04
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Описание:
Consider the following circuit involving a positive edge triggered D FF.
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Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period.
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Let A’ represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
(A) A0 A1 A1′ A3 A4
(B) A0 A1 A2′ A3 A4
(C) A1 A2 A2′ A3 A4
(D) A1 A2′ A3 A4 A5′
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