VSORA Is Redefining AI Inference & Designing High-Efficiency AI Processors Using Cadence Solutions

Описание: Reduce the cost of AI inference. Discover how VSORA’s Jotunn 8 and Tyr processors use a new silicon architecture to maximize efficiency with Cadence EDA tools

The primary hurdle facing the semiconductor industry today is the high cost of AI Inference. As major companies invest billions into building Data Center infrastructure, the need for Processing Efficiency has become the defining factor for profitability. VSORA addresses this by offering high-performance Chips for AI that significantly reduce the Cost per query and Cost per token. This architectural shift is designed to enable the Mass deployment of generative AI, making high-processing power accessible for both enterprise servers and localized edge devices.

VSORA’s approach is centered on a fundamental revision of Data Movement. Traditional chips often suffer from "data starvation," where the processing units sit idle while waiting for information. VSORA’s New architecture in silicon solves this by:

1. Arithmetic Unit Efficiency: Completely revising the internal flow to feed every Arithmetic unit with data at each cycle, ensuring a significantly higher Utilization rate than conventional designs.

2. Embedded Memory Scaling: Integrating a high level of Memory embedded in the chip to handle the vast weights of modern Neural networks without the latency and power penalties of off-chip communication.

3. Market-Specific Design: Utilizing the Jotunn 8 for data center cost-reduction and the Tyr product line for Edge AI applications like Autonomous driving.

To bring these complex AI Inference chips to life, VSORA leverages the Full system simulation capabilities provided by Cadence. This collaboration covers the entire lifecycle of the chip, from the Advanced technology node to the final Board design.

• Core Implementation: Using Xcelium for high-speed RTL simulation, Genus for Synthesis, Modus for DFT and ATPG and Innovus for the physical implementation.

• Connectivity & Integrity: Integrating PCIe Gen 5 IP for a High speed interface, while utilizing Allegro and Sigrity for Signal integrity simulation on the PCB.

• System Verification: Running long-running Emulations on the Palladium platform, which is accessed via the Cloud for maximum flexibility.

• Design Expertise: Partnering with the Cadence Design services team to handle complex Physical implementation and DFT insertion.

Video Highlights & Timestamps :

0.05 – Redefining AI Inference: The Challenge of Data Center Costs
1.06 – Jotunn 8 vs. Tyr: Solutions for Data Center and Edge AI
1.39 – Silicon Architecture: A New Approach to Data Movement
2:18 – Collaborating with Cadence for Full System EDA Solutions
3:05 – High-Speed Connectivity with PCIe Gen 5 IP Integration
3:59 – Scaling Verification: Palladium Emulation on the Cloud
4:30 – Future Outlook: Next-Gen Advanced Technology Nodes

Also Asked Questions (ASK) :

1. What is the primary challenge VSORA is solving in AI?
VSORA is focused on reducing the high cost of AI Inference and the investment required for Data Center deployment by increasing Processing Efficiency.

2. How does VSORA’s architecture differ from competitors?
They have revised Data Movement logic to feed every Arithmetic unit with data at every cycle, resulting in a much higher Utilization rate.

3. Which Cadence tools are used for PCB and Board design?
VSORA uses Allegro for Board design and Sigrity for Signal integrity simulation of the PCB.

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