Design Integration: Systematic Identification of Key Design Factors for Chiplet Eco System Enabling

Описание: Road to Chiplets - Design Integration
Systematic Identification of Key Design Factors for Chiplet Eco System Enabling
Thomas To
AMD

With so many features of interest at play in computing, adding all the features of interest in the most advanced silicon process node to meet the ever growing computing demand is very challenging. Chiplet implementation uses a selection of modular dies, referred to as chiplets, to provide a heterogeneous integration approach and to offer best-in-class feature combination. However, identifying the key system design factors to enable a successful system is complicated.

In this report, a design factor sensitivity methodology will be presented. Chiplet system channel jitter is used as the desired optimized result and the impacts of different design factors on the result are examined.

Based on a behavior jitter model, this method first correlates the model to an actual measurement of a High Bandwidth Memory (HBM) system.

The model is then extended to represent different input factors for the system output data path jitter. These input factors include the multiple supply power frequencies, their corresponding noise amplitudes, signal transition slew rate, as well as channel routing configurations such as different ground signal configurations. A set of output jitter response surface model, with different power tone frequencies and noise amplitudes, is then developed, with an optimal channel interconnect. The response surface model provides a contour to identify critical input parameters such that system platform designers can evaluate the effects of multiple input factor and their interactions. This approach allows for a holistic consideration for optimizations & specification.