AMD Spartan™ UltraScale+™ SCU35 Technical Reference Design

Описание: This demonstration provides a brief overview of the “Spartan UltraScale+ SCU35 Technical Reference Design”.

In this walkthrough, you will explore the AMD Spartan UltraScale+ SCU35 Evaluation Kit and build the SCU35 IO Technical Reference Design (TRD). You will generate the hardware platform in the AMD Vivado™ Design Suite, develop and build the standalone software application in the AMD Vitis™ Unified IDE, create the device image, and finally run and validate the design on the target hardware.

AMD Spartan UltraScale+ FPGAs deliver industry-leading I/O density—providing 3.5x more I/O per logic cell than previous Spartan generations—alongside low power consumption and robust security features. Built on a 16nm process node, these devices include hardened IP for DDR and PCIe on larger configurations, significantly improving interface efficiency.

The SCU35 evaluation board serves as a comprehensive hardware platform for implementing and validating these advanced capabilities in real-world scenarios. Specifically engineered for the Spartan UltraScale+ XCSU35P device, the board leverages high I/O counts and low-power operation, making it ideal for industrial, medical, and other high reliability sectors.

https://www.amd.com/en/products/adapt...

SCU35 IO Technical Reference Design Instructions (XD333) - https://docs.amd.com/r/en-US/xd333-sc...

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