NextSilicon at

Описание: NextSilicon ‪@nextsilicon‬ is pitching a computing stack that tries to keep legacy HPC code relevant while pushing more work into a dedicated accelerator, instead of forcing every team to rewrite kernels for a new API. In this interview, Dan (principal engineer) frames the goal as “seamless acceleration”: take existing C/C++/Fortran, recompile with a thin LLVM-based toolchain wrapper, and let the compiler carve out regions that map onto the device. https://www.nextsilicon.com/

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Product one is Arbel, a high-performance RISC-V CPU core taped out on TSMC 5 nm, positioned as the latency-focused counterpart to the accelerator. The design emphasis is classic out-of-order speculation and high IPC: a very wide front end (10-wide decode is called out), deep instruction windows, and aggressive scheduling to shrink the serial portion of real code at runtime.

Product two is the Maverick dataflow accelerator, where parallel work is represented as a dataflow graph and “projected” onto hardware to build pipelines and duplicate projections for more throughput. The booth signage mentions figures like 20× over CPU and 4× over GPU, but the deeper point is the compilation path: no wholesale rewrite, just recompilation and automatic graph mapping to the device graph.

The hardware story matters too: Gen1 is already deployed for evaluation in several national labs, and Gen2 expands into both single-die PCIe cards (roughly 350 W class) and a higher-power dual-die module coupled with HBM, linked die-to-die to behave like a larger logical device. Partners shown include rack-scale systems and OAM-style platforms (with names like HP, Dell, and Penguin Computing) that attach multiple cards behind one host CPU in a standard server footprint card.

A useful lens here is Amdahl’s law: even “perfect” accelerators stall on the stubborn serial fraction, so pairing a strong CPU core with a throughput machine can raise the ceiling without pretending everything is embarrassingly parallel. Filmed on the SC25 Supercomputing show floor in St. Louis, the conversation lands on developer ergonomics for MPI/OpenMP teams, vectorized kernels, and long-lived codebases that want more FLOP/W without starting from zero in a new programming model there.


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