Utilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling

Описание: By Nicolas Delemarre, Field Application Engineer & Technical Manager, Lauterbach.

Abstract: This presentation explores the use of RISC-V trace standards to improve debugging and profiling efficiency in modern embedded systems. As chip architectures and embedded systems grow increasingly complex, developers face significant challenges: more powerful multicore processors in various configurations (SMP, AMP), diverse operating systems (Linux, AUTOSAR, …), and heterogeneous multicore architectures that increase debugging requirements. The ‘RISC-V External Debug Support’ specification v1.0.0 offers a comprehensive solution for both simple and complex debugging scenarios, with flexibility to adapt to the most diverse SoCs. The presentation will demonstrate how trace tools leverage these standards to facilitate RISC-V system debugging and optimize application performance.

Bio: Nicolas Delemarre joined Lauterbach in 2018 and serves as both Field Application Engineer and Technical Manager for the French subsidiary. With a degree in Embedded Systems, he is a TRACE32 expert specializing in Arm and RISC-V architectures. As Technical Manager, Nicolas oversees all customer technical support, training, and services. During his six years at Lauterbach, he has assisted hundreds of clients across various platforms and developed custom OS awareness packages for French customers. Nicolas is passionate about solving complex problems and understanding systems “under the hood.” His expertise in RISC-V makes him a valuable resource for customers navigating this open instruction set architecture. Outside of work, he contributes to open-source projects and develops personal Cortex-M based systems, continuously expanding his embedded systems knowledge.