DDCO LAB BCS302 for basic logic gates using verilog HDL code, progrsmming model is Structural model

Описание: Today's lab basic program with output waveforms verifying with truth table.

AND gate with truth table.

These types of basic programs are not in your syllabus, but i have written these programs to make you better understand the concept.

Here is a basic explanation and practical demonstration for an AND gate, including its program, truth table, and how the output waveform verifies the logic operation.

AND Gate: Basic Description
An AND gate is a fundamental digital logic gate that outputs HIGH (1) only when all its inputs are HIGH. If any input is LOW (0), the output is LOW (0)

Truth Table for AND Gate

| Input A | Input B | Output Y (A AND B) |
|---------|---------|--------------------|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

This table shows all possible input combinations and their corresponding output, verifying the logical behavior of the AND gate

Basic Lab Program for AND Gate (Example in Verilog)

```verilog
module and_gate(a, b, y);
input a, b;
// Declare inputs
output y;
// Declare output
assign y = a & b;
// AND operation
endmodule
```
This program defines a module with two inputs (a, b) and one output (y) where 'y' is the logical AND of 'a' and 'b'

Output Waveform and Verification

When simulating or executing this program with all four input combinations, the waveform will show the output high (1) only when both A and B are high (1).
For example:
A=0, B=0 → Y=0
A=0, B=1 → Y=0
A=1, B=0 → Y=0
A=1, B=1 → Y=1

This matches the truth table, verifying the AND gate operation practically and visually using timing diagrams


Purpose of These Basic Programs

While such simple gate experiments may not always be part of standard university syllabi, practicing with them helps in developing a deeper conceptual understanding of digital logic and its real-world applications.