Verify your Next AI/ML design with Questa One Avery VIP

Описание: As AI and machine learning designs grow more complex, so does the challenge of verifying the advanced protocols that make them work. In this session, Gordon Allen, Director of Product Management for Verification IP at Siemens EDA, explores how Questa™ One Avery Verification IP is helping design teams verify next-generation compute and connectivity standards efficiently and accurately.

Through the video Gordon highlights how Questa™ One Avery VIP integrates with Questa One and Verification IQ, delivering a connected, scalable, and data-driven flow that optimizes productivity. From compliance test suites to regression management and coverage closure, Siemens EDA offers engineers a complete solution for faster debug, higher coverage, and greater design confidence.

Timestamps

0:00 – Introduction: Gordon Allen, Siemens EDA
0:17 – The growing verification challenge in AI/ML design
0:45 – Key high-performance compute protocols (PCIe Gen7, Ultra Ethernet, UAI Link)
1:10 – Overview of Questa™ One Avery Verification IP
1:35 – Integrating AI/ML capabilities into Questa One
13:44 – Inside Siemens’ compliance test suite approach
15:18 – Managing complex verification with Verification IQ
16:46 – Real-world examples: PCIe and Ethernet ecosystems
17:04 – Closing remarks and further resources


Verification isn’t just a technical step — it’s the key to innovation.
Learn more about Questa™ One Avery Verification IP and how Siemens EDA is advancing high-performance compute verification for AI/ML designs.

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