Ross G Daly (Stanford) Constructing and Using Families of Hardware Accelerators

Описание: UCSC Open Source Hardware and EDA Seminar

Due to the end of Moore’s Law and Dennard Scaling, future performance increases are likely driven by the increased hardware efficiency of domain specific architectures and accelerators. In this new golden age of computer architecture, we would like to quickly iterate over different viable architectures, but evaluating performance of a particular architecture using real applications requires a custom compiler, usually manually coded, slowing down this iteration. In this talk I will describe the Stanford Agile Hardware (AHA) group’s approach to accelerate image processing and DNN applications using a meta-compilation framework jointly generating the accelerator and the accelerator’s compiler.