Exploring New Architecture with Special Neural CPU and Compute-in-Memory Design, Jie Gu
Автор: Samsung Semiconductor Innovation Center
Загружено: 2021-01-21
Просмотров: 802
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As Moore's law stalls, novel computing solutions are urgently needed to meet the large computing demands from machine learning tasks on resource-constrained edge devices. This talk will elaborate our recent efforts in creating new dimensions in architecture and circuit solutions. In the first topic, we will discuss a special “neural CPU” architecture where a binary neural network is used to emulate RISC-V CPU showing significant benefits in computing latency and silicon cost. In the second topic, we will further explore mixed-signal compute-in-memory design with a special 3T “analog memory” rendering the state-of-art energy efficiency for CNN accelerators.
Jie Gu is currently an assistant professor in Northwestern University. He received his B.S. degree from Tsinghua University, M.S. degree from Texas A&M University and Ph.D. degree from University of Minnesota. From 2008 to 2010, he was a researcher at Texas Instruments, Dallas, TX on the design of ultra-low power mobile processors for smartphones. From 2011 to 2014, he was a senior staff member at Maxlinear leading developments of home multimedia broadband SoC chips. He joined Northwestern University from 2015 working on energy efficient circuit and architecture for modern microprocessors and machine learning accelerators. He is a recent recipient of NSF CAREER award.
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