How to Control 7-Segment Displays on Basys3 FPGA using Verilog in Vivado
Автор: FPGA Discovery (Learning How to Work with FPGAs)
Загружено: 2022-03-06
Просмотров: 28225
Описание:
Using the Digilent Basys3 reference manual and a demonstration circuit implemented on the FPGA, just wanted to explain the logic behind driving the 7-segment displays on the Basys3, such as I have done in previous videos.
UPDATE: The calculation for the 1ms refresh period is not accurate. For the refresh period the calculation should consider the following:
A 100MHz clock has a period of 10ns, that is 10 x 10^-9 seconds or 1 second / 100,000,000. Therefore, to achieve a period of 1ms, 10ns is multiplied by 100,000. So, 100,000 ticks of the 100MHz clock is equal to 1ms. So, for example, to achieve a refresh period of 2ms the calculation for the digit_timer should be 10ns x 200,000 = 2ms. So, 200,000 ticks of the 100MHz clock is a period of 2ms. So, for a 2ms digit refresh period, the digit_timer would count to 199,999 and then reset and switch to the next digit_select. Sorry for the confusion.
Find all files at
https://github.com/FPGADude/Digital-D...
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