ITC 2025 - Special Session 9D - Best Paper from ITC India 2025 - 259 - AASTM - Intel Foundry - DrGSJ

Описание: This study presents an accelerated aging analysis of
a classic bandgap reference (BGR) circuit to evaluate its reliability
and performance over time. Implemented on a Quality and
Reliability On-Chip (QROC) platform, the BGR demonstrated
a temperature coefficient of 0.12 mV/°C from 25°C to 100°C,
ensuring stable operation across temperature variations. The
output reference voltage (Vref ) remained at 646 mV across a
supply range of 0.8 V to 1.4 V, with a variation of ± 7.5 ppm/V.
After a one-million-second stress test at elevated temperatures
and 1.4 V stress voltage, Vref shifted by only 1%, showing less
than 6.5% deviation from post-layout simulations, confirming the
circuit’s robustness and long-term precision.

IEEE Keywords - band gap reference BGR, aging, quality and reliability,
accelerated aging stress
#BandGapReference #BGR #Aging #quality #reliability #reliabilityengineering #stress #siliconstress #design #stability #optimization #PVT #Variability
#analogelectronics

Technical Analysis & Review
Core Subject: The presentation focuses on the Accelerated Aging Stress Test Methodology (AASTM). This involves stressing circuits with high voltage and temperature over time (up to 1 million seconds) to predict long-term performance degradation [04:46].

Key Innovation: The use of the QROC (Quality and Reliability on Chip) platform, which features over 300 I/Os and 15,000+ ring oscillator instances to evaluate reliability mechanisms like thermal breakdown and latch-up [02:15].

Findings: The study showed a high correlation between silicon results and simulations (Siltosim). The BGR circuit proved robust, showing only a 1% degradation in reference voltage under extreme stress conditions [12:38].

Presentation Style: The style is academic and professional, typical of a premier engineering conference. It follows a logical flow: Problem statement - Methodology - Results -Conclusion [00:54].

#IntelFoundry , #FinFET #reliability, #SiliconLifecycleManagement (SLM), #analogicdesign Design, BGR reliability, and ITC 2025. #intel

[00:00] - Introduction and Presentation Opening

[00:54] - Reliability Challenges in Advanced Technology Nodes

[02:15] - Overview of the QROC (Quality and Reliability on Chip) Platform

[03:54] - Reliability Mechanisms (HCI, BTI, and TDDB)

[04:46] - AASTM: Accelerated Aging Stress Test Methodology

[06:50] - Case Study: Band Gap Reference (BGR) Circuit Design

[08:52] - Pre-Stress vs. Post-Stress Measurement Results

[10:14] - Detailed Analysis of Reference Voltage (Vref) Degradation

[11:34] - Silicon vs. Simulation (Sil2sim) Correlation

[12:38] - Summary and Conclusion

[13:30] - Closing Remarks and Acknowledgments