Behavioral Modeling in HW/SW Co-design Using C++ Coroutines - Jeffrey Erickson, Sebastian Schoenberg

Описание: https://cppcon.org/
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Behavioral Modeling in HW/SW Co-design Using C++ Coroutines - Jeffrey Erickson & Sebastian Schoenberg - CppCon 2023
https://github.com/CppCon/CppCon2023

Faced with the challenge of modeling a hardware IP that is controlled by a processor running C code, we developed two key methodologies that we want to share with the C++ community. The first is “Register Hooking”, where we use the preprocessor to alter the behavior of primitive data type interactions to allow for a model interaction without extensive code alteration. The second methodology is the use of coroutines to define side effects through behavioral models, which constitutes the majority of this talk.

Coroutines have the advantage of representing the parallel nature of hardware in a syntactically friendly way. Using coroutines also avoids several potential synchronization problems that arise with multi-threaded approaches or extensive and nested use of async/future. Complex hardware interactions can be represented with relative ease using coroutines.
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Jeffrey Erickson

Jeffrey E Erickson works in HW/SW Codesign Architecture in the Programmable Solutions Group at Intel Corporation. He holds a BS in Electrical and Computer Engineering from the University of Virginia and a doctorate from Rutgers University and UMDNJ. For 15 years he has worked in embedded systems development including FPGA-processor integration, secure firmware development, and systems modeling. He holds 3 patents in image processing and signal integrity.

Sebastian Schoenberg

Sebastian Schoenberg is a Principal Engineer at Intel Corporation and responsible for Intel’s FPGA and eAsic firmware software architecture. After completing his PhD in computer science at the University of Technology in Dresden, Germany, Sebastian joined Intel’s Research Labs where he applied his micro-kernel and real-time operating system background to develop modern hypervisor software architectures to help define Intel’s Virtualization Technology Hardware Architectures. During his time at Intel’s Internet of Things group, Sebastian was driving information-centric network and distributed IoT edge computing software architectures for next generation smart IoT applications and scalable IoT device onboarding capabilities. Sebastian holds 30+ patents in the area of virtualization, Internet of Things and Information Centric Networking.
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Work at Hudson River Trading (HRT): https://tinyurl.com/safxfctf
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