Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA
Автор: RISC-V International
Загружено: 2021-12-13
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Algorithm Acceleration for RISC-V Processors using High-Level Synthesis - Russell Klein, Siemens EDA
Increasing the performance and efficiency of a RISC-V designs can be done by moving compute intensive functions from software, running on the CPU, into hardware accelerators. These accelerators can take the form of new instructions, co-processors, or bus based peripherals. One way to create this type of accelerator is to use High-Level Synthesis (HLS). HLS takes a C or C++ function and synthesizes a functionally equivalent Register Transfer Level (RTL) hardware description. This RTL description can be used to create the hardware accelerator for an ASIC or FPGA. This session will show you how to create different types of accelerators using HLS and how to integrate them into RISC-V processor designs. An AI inferencing algorithm and a an encryption algorithm will be used as examples to show how the accelerator can impact the performance and power consumption of a RISC-V design.
For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: https://riscv.org/
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