ZYNQ Ultrascale+ and PetaLinux (part 12): FPGA Pin Assignment (LVDS Data Capture Example)
Автор: Mohammad S. Sadri
Загружено: 2020-10-20
Просмотров: 6761
Описание:
In this video we go through a simplified example design which transfers data between two chips at a total rate of ~ 5 GBits/s using LVDS signals. We look at how pin locations can affect the final timing of the design.
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