Day2 | D Flip-Flop (DFF) in Verilog | No Reset, Sync Reset & Async Reset Explained | RTL + Testbench

Описание: Link: https://edaplayground.com/x/Urxx

🧠 D Flip-Flop (DFF) in Verilog HDL | Day 2 - RTL Design + Testbench

In this video, we explore the D Flip-Flop (DFF) design with:
✅ No Reset
✅ Synchronous Reset
✅ Asynchronous Reset

We write the *RTL code**, create the **testbench**, and analyze the **simulation waveform* step by step.

📌 This is part of the VLSI Beginner Series - ideal for:
RTL Design learners
Verilog HDL practice
VLSI interview prep (Qualcomm, Intel, etc.)
FPGA/ASIC developers

💡 Covered:
🔸 Differences between sync and async resets
🔸 Verilog `always @(posedge clk)` usage
🔸 Reset behavior in simulation

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