Implementing Gigabit Ethernet on FPGA with MicroBlaze and MIG - Part 1: Vivado Design

Описание: how to design a complete Ethernet system using MicroBlaze processor, AXI DMA, DDR memory interface, and Gigabit Ethernet IP core.

MicroBlaze Configuration: Setting up the soft-core processor with real-time presets, cache configuration, and local memory allocation

Memory Interface Design: Implementing MIG (Memory Interface Generator) for DDR3 access and connecting data/instruction caches

Peripheral Integration: Adding UART, timer, and interrupt controllers for a complete embedded system
Ethernet Implementation: Configuring AXI Ethernet IP with RGMII interface, PHY connection, and MDIO communication

DMA Setup: Implementing AXI DMA for efficient data movement between DDR memory and Ethernet interface without CPU intervention

Clock and Reset Management: Proper clocking strategy using 125MHz and 200MHz clocks with synchronized reset distribution

Board-Specific Configuration: Utilizing Xilinx AC701 evaluation board examples and automatic pin assignment

Key timeline:
00:00 - Introduction to Gigabit Ethernet protocol
03:51 - Vivado Block design with MicroBlaze and Peripherals
07:01 - Vivado design
07:20 - Adding MIG to the design
08:20 - Adding MicroBlaze to the design
10:36 - MicroBlaze connection to MIG DDR
11:18 - Connecting AXI timer and UART to MicroBlaze
14:00 - AXI Gigabit Ethernet configuration
16:57 - Routing Interrupts to the MicroBlaze
19:00 – I/O planning and schematic comparison