Hard Core and Soft Core Processors Implementations: Clearly Explained

Описание: We come across Hard Cores and Soft Cores very often in the FPGA design and Development.

Softcore does not imply that it can only be implemented on FPGA. It just means it is licensed as synthesizable HDL (Verilog/VHDL) code. The buyer can synthesize it into ASIC as well using ASIC libraries. And In the video, I have discussed the pros and cons when this soft-core is mapped (or implemented) on ASICs (as hardcore) vs. on FPGA.
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A slight mistake I made during the video, which led to some confusion among some viewers. So this is some Further Explanation of Soft Core and Hard Core.

A soft-core processor is delivered in the form of synthesizable HDL (Verilog/VHDL) code. This HDL code of soft-core can be customized for a given application and can also be synthesized for both an ASIC or FPGA target.

1) In the ASIC design flow, this HDL code can be synthesized using ASIC libraries. And after fabrication, it eventually leads to an ASIC (physical chip or a hardcore).
Once it becomes a hardcore (ASIC), At this stage, any customization in the Processor architecture will not be possible.

2) On the other hand, if the same HDL Code(Softcore code ) is implemented using FPGA, it is (in most cases) possible to change/customize the processor architecture in code and re-implemented the design on FPGA ( as FPGAs are reprogrammable.)

3) Softcore does not imply that it can only be implemented on FPGA. It just means it is licensed as synthesizable HDL (Verilog/VHDL) code. The buyer can synthesize it into ASIC as well using ASIC libraries.

e.g., Cadence provides Tensilica Processor IP as a soft-core. These soft cores can be implemented on both ASICs and FPGAs as well.

4) In the video, I have discussed the pros and cons when this soft-core is mapped (or implemented) on ASICs (as hardcore) vs. on FPGA.

5) And if you plan to write your own processor core in synthesizable HDL (Verilog/VHDL) code. You have the choice to either follow the ASICs design flow and make a Physical Chip or Implement it on FPGA. Both things are possible.

Thanks a lot for understanding.

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Timestamps:
0:00 Intro
0:30 Hard Core Processor
2:57 Soft Core Processor
7:40 Open Source and Commercial Soft Cores