Morpheus – A Unified Neuromorphic Framework
Автор: Aviral Dwivedi
Загружено: 2026-02-22
Просмотров: 58
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Presentation used in this video
Google Drive:
https://drive.google.com/file/d/1LhkZ...
GitHub Repositories
Neurom Simulator
https://github.com/Aviral-Dwivedi06/N...
Neurom Predictor
https://github.com/Aviral-Dwivedi06/N...
Neurom Recommender
https://github.com/Aviral-Dwivedi06/N...
Neurom Explorer
https://github.com/RockingAayush/Data...
We have developed and designed Morpheus which is a mixed signal neuromorphic
processor that integrates a reconfigurable digital backend with
a multilevel memristive synaptic crossbar. The analog front
end performs in memory vector matrix multiplication using
summing amplifier based current integration, while a VCO
based column ADC converts accumulated synaptic currents into
digital form. The digital backend implements leaky integrate
and fire LIF neurons, spike driven computation, and simplified
STDP learning. We introduce adaptive SSR mechanisms and
dual bank weight SRAM to optimize performance. Experimental
validation demonstrates robust operation under device variability
and efficient memory centric mixed signal computation
We worked on the below architectures as part of our efforts to create Morpheus (A Unified Neuromorphic Framework) :-
• Memristive crossbar based VMM
• Summing amplifier current integration
• VCO based ADC with asynchronous counters
• Adaptive SSR with zero skipping for sparse processing
• Dual bank SRAM for concurrent learning
• Digital LIF neurons with on chip learning
The architecture demonstrates scalable, energy efficient
mixed signal computation suitable for future neuromorphic
hardware platforms
To accelerate design-space exploration and data handling
for this mixed signal work, we developed and leveraged
four auxiliary ML toolchains: (1) NeuroM-Predictor which trains
regressors on device and circuit sweeps to predict crossbar
IR-drop, ADC ENOB, and PE utilization without rerunning
full SPICE RTL co-sim; (2) NeuroM-Recommender which ranks
neuromorphic configurations subject to BRAM, LUT, and
latency constraints, providing Pareto-front options for SSR
depth, SRAM banking, and cache sizes; (3) NeuroM-Simulator
which offers a fast behavioral loop that mirrors the mixed
signal pipeline—crossbar read, VCO quantization, SSR scan,
PE accumulation—and emits cycle-accurate activity traces
used to size guard times and integration windows; and (4)
Datasheet-Explorer which automates component selection and
parameter extraction from vendor datasheets, feeding clean
priors (slew limits, noise floors, timing) into the ML predictors.
Collectively these assets reduced iteration time and grounded
the architectural choices reported here .
To conclude, we have created Morpheus which is a Unified Neuromorphic Framework. The construction and implications of Morpheus span across various domains such as analog electronics, digital electronics and machine learning.
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