Electronic design automation (EDA)

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Place-and-Route (P&R) – The automated process of positioning standard cells on a chip layout and routing interconnections between them.

Netlist – A representation of an electronic circuit that lists all components and their connectivity.

Static Timing Analysis (STA) – A method for verifying circuit timing performance without simulation by checking worst-case delays.

Design Rule Check (DRC) – Automated verification that a physical layout complies with foundry manufacturing constraints.

Layout Versus Schematic (LVS) – A verification process that ensures the physical layout matches the intended schematic design.

Formal Verification – Mathematical proof-based verification ensuring logical equivalence between RTL and synthesized designs.

Technology Mapping – The process of converting a technology-independent logic network into a gate-level netlist using a specific standard cell library.

Clock Tree Synthesis (CTS) – Automated construction of a balanced clock distribution network to minimize skew.

Scan Insertion (DFT) – The addition of test structures to a design to enable Design-for-Testability (DFT).

Parasitic Extraction (PEX) – The process of modeling parasitic resistances, capacitances, and inductances from a layout to improve simulation accuracy.