Synchronization (DiHALT 2015 - 1,ZX Enhanced Demo) ZX Evolution + TS Conf [8K, 50fps]

Описание: This video recorded on 11March2021

Attention! In order not to miss the details of the video, as well as some effects-it is strictly recommended to run this video with a quality of 50 fps (720p50fps, 1080p50fps and higher).

Name of the program: Synchronization
Categories: Demo, Demoscene
Supported languages: English
Produced by: CONSCIOUSNESS (Ukraine)
Release date: 04 July 2015
Competition: Di Halt 2015 (1, ZX Enhanced 8-Bit Demo Compo)
City: Nizhniy Novgorod [Nizjnij Novgorod], Russia

Authors:

TS-Labs - Coding [FPGA]
Hacker VBI - Code
Rob F. - Code
n1k-o (Nq, Oleg Nikitin) - Music
Brightentayle - Graphics
Mellona - Graphics
Nodeus - Graphics

TurboSound (2xAY: 6 channels) used in this demo
Soundtrack version for 1xAY (original ZX Spectrum):
http://zxart.ee/eng/music/authors/n/n...

Soundcloud:   / synchronization  

https://zxart.ee/eng/software/demosce...
http://zxdemo.org/productions/166597/
https://demozoo.org/productions/142487/
https://www.pouet.net/prod.php?which=...

Hardware:
This is a custom FPGA config for ZX-Evolution board. It supports sprites, tiles, scrollers, color-per-pixel graphics, DMA, blitter, 14MHz CPU clock. All magic - is a carefully selected set of HW features which managed to fit into 2880 LCs of ZXE chipset.
It is ported to Reverse series (also FPGA), Speccy 2010 boards. ZX (exactly Pentagon 512 clone) is taken as a baseline, thus all Pentagon software works on it, hence - ZX category, as soon as here is no separate category for it.

Limits are:
up to 286720 CPU T-states per frame
4 MB DRAM
85 sprites per line, 8x8 up to 64x64 pixels size, 15 colors, any of 16 palette set, 3 layers
2 tile planes with up to 4096 tiles 8x8 pixels size
256/16 colors per pixel 512x512 pixels screen with movable window (=screen scroller), looped inside addresses
texmod up to 90x36 chars within 16kB page, 2kB font at adjacent page
256 shared indexed colors CRAM, 32k (RGB555) color space
448 DRAM cycles per line, dinamically distributed, from which any cycle may be:
--- 2 CPU bytes
--- 4 sprite/tile pixels, or 4 16 color pixels, or 2 256 color pixels
--- 1 DMA 16 bit access.
AY-3-8910/YM-2149 and 8 bit DAC
Frame (movable), Line and DMA masked CPU interrupts
and of course ZX compatible 6912 screen ;)

Other works on Di Halt 2015:
https://demozoo.org/parties/2514/
https://www.pouet.net/party.php?which...

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