DVD - Lecture 11a: Sign-off Timing
Автор: Adi Teman
Загружено: 2022-10-25
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Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 11 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 11 wraps up the RTL to GDS flow with the extra steps that are needed to take a design that has finished place and route and prepare it for tape-out.
Lecture 11a revisits Static Timing Analysis for signoff, applying additional timing margins, discussing concepts, such as on-chip variation (OCV) and its flavors.
Lecture slides can be found on the EnICS Labs web site at:
https://enicslabs.com/academic-course...
All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University
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