Instruction Set Architecture - x86, ARM and RISC-V | Embedded systems podcast, in Pyjama

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𝗜𝗻 𝘁𝗵𝗶𝘀 𝗩𝗶𝗱𝗲𝗼:
We chat about the instructions set architecture, what it is, why we care about it, and where it becomes relevant.

Intel Architecture ISA document: https://cdrdv2-public.intel.com/78958...
ARM Architecture: https://cdrdv2-public.intel.com/65420...
RISC-V ISA Manual: https://riscv.org/wp-content/uploads/...

𝗧𝗮𝗯𝗹𝗲 𝗼𝗳 𝗰𝗼𝗻𝘁𝗲𝗻𝘁𝘀
00:00 Topic for today
00:24 Introduction to Instruction Set Architecture (ISA) and Why We Care?
02:08 Relation between CPU and ISA
03:50 CISC vs RISC Architecture - Instruction Decoding
06:32 CPU and Registers
07:18 The need for ISA - The abstraction layer
09:12 Back to CISC vs RISC
09:37 Exploring the relation between architecture and instructions
11:40 Assembly instructions and ISA
13:25 Directives in assembly language
14:03 RISC architecture and effect on instruction count and formatting
15:41 What does "Reduced" in RISC really mean?
17:38 Dev presents his understanding
18:26 Venturing into different types of ISA - x86, ARM, RISC-V
19:34 ARM and RISC-V architecture
20:33 ARM as a company and its business model
23:52 Background of RISC-V, Royalty, and crossing the boundary and drifting...
28:44 Back to the story of the Origin of RISC-V
29:51 Ratification and Idea of ISA Extensions
30:31 Integer Extension - The minimum instructions to be implemented to be called RISC-V
31:01 More about the idea of extensions to the ISA
32:05 Intel x86 ISA
35:00 CISC, Memory Speed and the influence on the CPU design
36:36 ISA and effects on the complexity of Compiler
38:00 Example of CISC instruction - Find substring!
38:45 More on compiler design and abstractions - GCC and Clang
41:42 Detour: MIPS, SPARC etc architecture
43:33 The Story of Origin of ARM
45:57 Apple, ARM, and parts of the Origin Story.
48:39 Why Should an embedded engineer care about ISA?
49:27 Should the C/C++ programmer care?
50:24 When assembly shines - What cannot be done in C/C++
51:10 Implementing locks and the use of atomic instructions
52:30 Implementing scheduler and special instructions
55:17 Standards and abstraction - memory barrier for example
56:54 TECH GLITCH! (skip)
58:30 Back to architecture and effect on compiler design.
01:02:57 Rajat's work at ATMEL and the source code in Assembly
01:03:09 Assembly and Highspeed I/O
01:04:18 Converting C to assembly and optimizing it.
01:05:47 Accidental detour to wifi firmware... Linux and RTOS!
01:08:56 Internal discussion! (skip)
01:09:06 Closing thoughts

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