Verilog HDL Tutorial Part 17 | Variables in Verilog | reg Data Type Explained | Signed vs Unsigned

Описание: Verilog HDL Tutorial Part 17 | Variables in Verilog | reg Data Type Explained | Signed vs Unsigned

📌 Description

Welcome to AK APT LOGICS – Verilog HDL Tutorial Series 🎥

In Part 17, we explore Variables in Verilog HDL, focusing on the reg data type.
Unlike nets (which represent connections), variables represent storage elements that can hold values between assignments.

📖 Topics Covered

Difference between Nets and Variables

What is a Variable in Verilog?

reg Data Type Explanation

Signed vs Unsigned reg

Behavior of reg in simulation

Role of reg inside always blocks

Why output in always blocks must be declared as reg

📌 Key Points about reg

By default, reg stores 1 bit

Default value = x (unknown)

By default, reg is unsigned

reg can represent both combinational and sequential logic

Signed reg displays negative values correctly; unsigned reg shows 2’s complement value

📌 Example Code

module variable;
reg signed [3:0] a = -7;
initial begin
$display("a = %0d", a);
// If reg is signed → prints -7
// If reg is unsigned → prints 9 (2’s complement of -7)
end
endmodule


📌 Output
a = -7
→ Signed reg displays negative correctly
→ Unsigned reg prints 2’s complement (e.g., 9 for 4-bit representation)

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