GAL18V10B-10LP Programmable Logic ICs - Avaq

Описание: The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide a very flexible 20-pinPLD. CMOS circuitry allows the GAL18V10 to consume much lesspower when compared to its bipolar counterparts. The E2 technology offers high speed (less than100ms) erase times, providing the abilityto reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10eliminates the learning curve usually associated with using a newdevice architecture. The generic architecture provides maximumdesign flexibility by allowing the Output Logic Macrocell (OLMC)to be configured by the user. The GAL18V10 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,DC, and functional testing during manufacture. As a result, LatticeSemiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles anddata retention in excess of 20 years are specified.
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https://www.avaq.com/chip/gal18v10b-10lp