Видео с ютуба Iverilog
![HDL (iverilog, gtkwave), RTL synthesis using OpenLane CT4Assignment [7 bit ALU with NAND & ROL]](https://ricktube.ru/thumbnail/ylSGS9OKyuc/mqdefault.jpg)
HDL (iverilog, gtkwave), RTL synthesis using OpenLane CT4Assignment [7 bit ALU with NAND & ROL]

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