Tech Spot with Harish Goupale
Tech Spot is your source of learning that belongs to the VLSI Domain and is related to Digital Electronics concepts, Verilog, System Verilog, UVM, and RISC-V processors.
This channel will cover all the basics and advanced concepts of Digital Electronics.
The basics of Verilog and hardware design will be covered in this channel.
The basics and advanced concepts of System Verilog will be covered in this channel.
The basics and advanced concepts of UVM (Universal Verification Methodology) will be covered in this channel.
Subscribe to the channel now for high-quality videos focused on different areas of the VLSI domain
such as :
1)Digital Electronics
2)Verilog
3)System Verilog
4)UVM
5)Constraint of System Verilog
6)Assertion of System Verilog
7)RISC-V processor
8)Functional Verification
9)Power Aware (PA) Verification
10)Formal Verification
11)CPU Verification
SR Flip-Flop using NOR gate| RTL Design implementation of SR Flip-Flop using System Verilog|Electron
S R Flip-Flop using NAND gate| RTL Design implementation of SR Flip-Flop using System Verilog|harish
D Latch | Working, Functionality, and RTL Design using Verilog in Vivado|Digital electronics|Tech..
SR Latch using NAND Gate|RTL Design implementation of SR latch using Verilog|Harish Goupale|digital
Encoder | RTL Design Implementation of 8:3 Encoder by using System Verilog |tech spot|Harish Goupale
Encoder | RTL Design Implementation of 4:2 Encoder by using System Verilog |tech spot|Harish Goupale
Decoder |3:8 decoder by using system Verilog | 4:16 decoder by using Verilog | RTL code | Harish Gou
Gray to Binary Code Conversion | RTL Design Implementation in SystemVerilog|Tech Spot Harish Goupale
Binary to Gray code Converter | RTL design implementation using System Verilog|Tech Spot Harish Gou
Decoder | 1:2 decoder by using System Verilog | 2:4 decoder by using Verilog | RTL code of decoder
Demultiplexer Functionality |1:2 Demultiplexer using Verilog |1:4 Demultiplexer using system Verilog
RTL Design implementation of Full Subtractor using Verilog|full subtractor using two half subtractor
RTL Design Implementation of Half Subtractor by using Verilog |System Verilog half subtractor
RTL Design of Full Adder Implementation in Verilog | Full Adder using two half adder Verilog Code
RTL Design Implementation of Half Adder by using Verilog| Verilog Half Adder tutorial |HarishGoupale
Implementation of Positive and Negative Edge Triggered D Flip-Flop by using 2:1 Multiplexer |Harish
Positive and Negative Level sensitive D Latch by using 2:1 Multiplexer | Digital electronics |Harish
Positive Edge Triggered D flip flop Tutorial| Negative Edge Triggered D flip flop | Techspot|Harish
Positive Level Sensitive D Latch Basics| Negative Level Sensitive D Latch Functionality|harishGoupal
Verilog code for 4:1 MUX|4:1 Multiplexer Functionality & RTL Design in Verilog & SystemVerilog|haris
Selection statement of Verilog Tutorial|if-else and case statement of System Verilog|tech spot|haris
Verilog code for 2:1 MUX|2:1 Multiplexer Functionality & RTL Design in Verilog & SystemVerilog|haris
System Verilog Reduction Operators and Shift Operators in English |Verilog | techspot|Harishgoupale
System Verilog Relational operators and Bitwise operators in Hindi | System Verilog Coding|techspot
System Verilog operators| Arithmetic and Logical operators in Hindi| Tech Spot|Verilog|HarishGoupale
Verilog Operators Tutorial|Implementation of Verilog operators in RTL design|Tech Spot|harishgoupale
Systemverilog data types in English| Verilog data types|Systemverilog part3|tech spot|harish_goupale
Verilog initial block|Verilog always block|System Verilog initial and always block|code execution.
Verilog module implementation | System Verilog Module implementation| use of EDA | use of Vivado
Combinational and sequential circuit | Combinational & Sequental Procedural Block of Verlog and SV