IIS Technologies
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Workshop on Machine Learning and Internet of Things
Design and Analysis of Approximate Compressors for MultiplicationOutput
Preemptive Built In Self Test for In Field Structural Testing Out put
Low Latency High Throughput Systolic Multipliers Over for NIST Recommended Pentanomials Output
Exact and Approximate Algorithms for the Filter Design Optimization OUTPUT
ERSFQ 8 Bit Parallel Adders as a Process Benchmark Output
A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Out put
Modeling and Design of Series Voltage Compensator for Reduction of DC Link Capacitance in Output
Novel Control Method for Transformerless H Bridge Cascaded STATCOM With Star Output
Model Predictive Control Methods to Reduce Common Mode Voltage for Three Phase Output
A Multi-Input Bridgeless Resonant AC-DC Converter for Electromagnetic Energy Harvesting Output
A High Step Up DC to DC Converter Under Alternating Phase Shift Control for Fuel Cell Output
High Gain Zero Voltage Switching Bidirectional Converter With a Reduced Number of Switches OUTPUT
Implementation of a High Efficiency, High Lifetime and Low Cost Converter for an Autonomo..Output
Novel Single Switch Resonant Power Converter for Renewable Energy Generation Application Output
Hybrid Transformer ZVSZCS DC–DC Converter With Optimized Magnetics and Improved Power.. OUTPUT
A BL-CSC Converter-Fed BLDC Motor Drive With Power Factor Correction Output
A Comparative Performance Investigation of Single-Stage Dimmable Electronic Ballasts Output
Modeling and Controller Design of a Semi-Isolated Multi-Input Converter output
Cascaded Two Level Inverter Based Multilevel STATCOM for High Power Applications Output
An Enhanced Grid Current Compensator for Grid Connected Distributed Generation Output
A New 7 Level Symmetric Multilevel Inverter with Minimum number of switches Output
Cascaded Two-Level Inverter-Based Multilevel STATCOM for High-Power Applications
An Enhanced Grid Current Compensator for Grid-Connected Distributed Generation Under
VLSI Implementation of an Adaptive Edge Enhanced Color Interpolation Processor for Real Time Video
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common
Further Desensitized FIR Halfband Filters Output
High Throughput Finite Field Multipliers Using Redundant Basis FPGA and ASIC Imp Output
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Sca