Anish Saha

Hi, let's learn, grow & explore while having fun! 😉

My hobbies are to travel around the world, Be productive and Obviously solving CIRCUITS!!!

In my channel, I'll try to provide concepts, Strategy and Motivation mainly related to Electrical and Electronics Engineering which will help you to crack Interviews and Competitive exams like GATE in the related domains.


Goal : Teach students all over World ♥️



Credentials :
- 2+ years of Teaching Experience
- GATE 2022 EE AIR 170 in 3rd Year
- Analog Engineer
- B.E in EE from Jadavpur University


Timeline of my YouTube channel

First Video - 04/08/23
1k Subs - 16/09/23
5k Subs - 14/09/24
10k Subs - 13/08/25


**All the views on the channel are of my own, I do not represent any organization or company.

🔥Примечания к RevisionX для аналоговых и цифровых профилей СБИС

🔥Примечания к RevisionX для аналоговых и цифровых профилей СБИС
🔥Complete VLSI Roadmap with Free & Paid Resources!

🔥Complete VLSI Roadmap with Free & Paid Resources!
Struggling with VLSI Placements? || Anish Saha

Struggling with VLSI Placements? || Anish Saha
Which is Better: Digital or Analog VLSI Profile? || Career Scope & Opportunities || Anish Saha

Which is Better: Digital or Analog VLSI Profile? || Career Scope & Opportunities || Anish Saha
🔥RC Circuits Transient Response with Current Source | Analog VLSI Placement Interview Questions

🔥RC Circuits Transient Response with Current Source | Analog VLSI Placement Interview Questions
Best Way to Prepare for Campus Placements & Utilize Your Time || Anish Saha

Best Way to Prepare for Campus Placements & Utilize Your Time || Anish Saha
🔥100 Days Digital VLSI Roadmap with Free & Paid Resources!

🔥100 Days Digital VLSI Roadmap with Free & Paid Resources!
Top Skills Every VLSI Engineer Should Learn in 2025 || Anish Saha || PrepFusion

Top Skills Every VLSI Engineer Should Learn in 2025 || Anish Saha || PrepFusion
Multilevel Cache, Cache Inclusion Policy || Cache Memory || Digital VLSI || Anish Saha

Multilevel Cache, Cache Inclusion Policy || Cache Memory || Digital VLSI || Anish Saha
Block Replacement & Types of Cache Miss || Cache Memory || Digital VLSI || Anish Saha

Block Replacement & Types of Cache Miss || Cache Memory || Digital VLSI || Anish Saha
🔥Digital VLSI Mastery Course Roadmap || Complete Placement Guide || Anish Saha || PrepFusion

🔥Digital VLSI Mastery Course Roadmap || Complete Placement Guide || Anish Saha || PrepFusion
Hardware Implementation of Cache Mapping || Cache Memory || Digital VLSI || Anish Saha

Hardware Implementation of Cache Mapping || Cache Memory || Digital VLSI || Anish Saha
Assignment Solutions of Cache Mapping || Cache Memory || Digital VLSI || Anish Saha

Assignment Solutions of Cache Mapping || Cache Memory || Digital VLSI || Anish Saha
Set Associative Cache Mapping || Cache Memory || Digital VLSI || Anish Saha

Set Associative Cache Mapping || Cache Memory || Digital VLSI || Anish Saha
Questions in Direct Cache Mapping || Cache Memory || Digital VLSI || Anish Saha

Questions in Direct Cache Mapping || Cache Memory || Digital VLSI || Anish Saha
Direct Cache Mapping || Cache Memory || Digital VLSI || Anish Saha

Direct Cache Mapping || Cache Memory || Digital VLSI || Anish Saha
Cache Write Policies Assignment Solutions || Cache Memory || Digital VLSI || Anish Saha

Cache Write Policies Assignment Solutions || Cache Memory || Digital VLSI || Anish Saha
🔥Locality Of Reference, Avg Access Time || Cache Memory || Digital VLSI || Anish Saha

🔥Locality Of Reference, Avg Access Time || Cache Memory || Digital VLSI || Anish Saha
5(C) Control & Structural Hazards in Instruction Pipelining || Digital VLSI || COA || Anish Saha

5(C) Control & Structural Hazards in Instruction Pipelining || Digital VLSI || COA || Anish Saha
5(B) Hazards in Instruction Pipelining || Digital VLSI || COA || Anish Saha

5(B) Hazards in Instruction Pipelining || Digital VLSI || COA || Anish Saha
5(A) Basics of Instruction Pipelining || Digital VLSI || COA || Anish Saha

5(A) Basics of Instruction Pipelining || Digital VLSI || COA || Anish Saha
4(B) Microprogramming, RISC V/S CISC || Digital VLSI || COA || Anish Saha

4(B) Microprogramming, RISC V/S CISC || Digital VLSI || COA || Anish Saha
4(A) Datapath & Control Unit (CU) || Digital VLSI || COA || Anish Saha

4(A) Datapath & Control Unit (CU) || Digital VLSI || COA || Anish Saha
Complete Verilog Course Launch || Digital VLSI || Anish Saha || PrepFusion

Complete Verilog Course Launch || Digital VLSI || Anish Saha || PrepFusion
9. Verilog Exercises Solutions : Subtractor, Comparator, Counter, Synthesis | #30daysofverilog

9. Verilog Exercises Solutions : Subtractor, Comparator, Counter, Synthesis | #30daysofverilog
8(B) Verilog : Operators, Data Flow Modeling, and Examples | #30daysofverilog

8(B) Verilog : Operators, Data Flow Modeling, and Examples | #30daysofverilog
8(A) Continuous Assignments: assign Statement, Delays, and Concatenation | #30daysofverilog

8(A) Continuous Assignments: assign Statement, Delays, and Concatenation | #30daysofverilog
7. Verilog Assignment Solutions: Gate-Level Design, Latches, Multiplexers, Delay | #30daysofverilog

7. Verilog Assignment Solutions: Gate-Level Design, Latches, Multiplexers, Delay | #30daysofverilog
6. Verilog Gate Level Modeling Tutorial: Gates, Adders, Delays, and Simulation | #30daysofverilog

6. Verilog Gate Level Modeling Tutorial: Gates, Adders, Delays, and Simulation | #30daysofverilog
5. Verilog Exercises: Number Representation, Strings, Modules, Hierarchy | #30daysofverilog

5. Verilog Exercises: Number Representation, Strings, Modules, Hierarchy | #30daysofverilog