coe instructor

COE302-T251: Partitioning Digital Systems into Datapath and Control Unit: A Complete Example

An example of HPS/FPGA integration for DE1-SoC

Heron's Square Root Algorithm - Part 11

Heron's Square Root Algorithm - Part 12

Heron's Square Root Algorithm - Part 10

Heron's Square Root Algorithm - Part 9

Heron's Square Root Algorithm - Part 8

Heron's Square Root Algorithm - Part 7

Heron's Square Root Algorithm - Part 6

Heron's Square Root Algorithm - Part 5

Heron's Square Root Algorithm - Part 4

Heron's Square Root Algorithm - Part 3

Heron's Square Root Algorithm - Part 2

Heron's Square Root Algorithm - Part 1

Fixed-Point Numbers and Arithmetic

Complete Circuit Example: Hypotenuse Calculator 1/3

Complete Circuit Example: Hypotenuse Calculator 2/3

Complete Circuit Example: Hypotenuse Calculator 3/3

From ASM Chart to Verilog Code -- Cont'ed (3/3)

From ASM Chart to Verilog Code -- Cont'ed (2/3)

From ASM Chart to Verilog Code (1/3)

State minimization (1/2) (COE561 - Lecture of Sep. 21)

Advanced Verilog - Part 1

Similarity Transform Example 2 (4/4)

Similarity Transform Example 2 (3/4)

Similarity Transform Example 2 (2/4)

Similarity Transform Example 2 (1/4)

Similarity Transform Example

Similarity Transform

Algebraic Properties of Basic Rotation Matrices