MATLAB PROJECTS CODE

Dadda multiplier

multilevel

Duty

Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance

A dft insertion methodology to scannable Q Flop Elements xilinx

Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks xilinx

Parasitic Aware Automatic Analog CMOS Circuit HSPICE

Three Dimensional Pipeline ADC Utilizing TSV HSPICE

Key Switched Capacitor LPF with

Noise Figure Inductorless HSPICE

On Synthesizing Memristor Based Logic Circuits HSPICE

Multilevel Half Rate Phase Detector for Clock and Data Recovery Circuits HSPICE

Feedback Based Low Power Soft Error Tolerant Design HSPICE

Energy and Area Efficient Spin–Orbit Torque HSPICE

Dual Port 8T SRAM with Duplicated InterPort

Secure Double Rate Registers as an RTL HSPICE

Systematic Design of an Approximate Adder The Optimized HSPICE

Duty Cycle Based Controlled Physical HSPICE

An Electrical Model for Nanometer CMOS Device HSPICE

A Changing Reference Parasitic Matching Sensing HSPICE

CMOS Current Reversing Circuit

CMOS Oscillator having Stable Frequency with Process, Temperature hspice

DCMCS Highly Robust Low Power Differential HSPICE

A Dual Data Line Read Scheme for High Speed HSPICE

Area efficient NMOS based positive and negative HSPICE

Clock and data recovery HSPICE

An Ultra Low Power, 10 bit Two Step Flash ADC for Signal Processing HSPICE

A DfT Insertion Methodology to Scannable Q Flop Elements HSPICE

CMOS Gates with Second Function hspice

Design of Divider Circuit for Electrochemical Impedance Spectroscopy HSPICE